SRAM cells (or SRAM cell structures) in general are random access memory cells that retain data bits in their memory as long as power is being supplied. SRAM is used in personal computers, workstations, routers, peripheral equipment and the like.
SRAM cells are composed of a pair of cross coupled inverters connected together by a pair of cross-coupled contacts to form first (1st) and second (2nd) storage node outputs with opposing logic states. Therefore SRAM cells have two stable logic states. The first logic state includes a logic one (1) and a logic zero (0) at the 1st and 2nd storage node outputs, respectively. The second logic state includes a logic 0 and a logic 1 at the same 1st and 2nd storage node outputs, respectively. The storage nodes will be connected to a pair of pass gate transistors, which are usually n-type transistors.
Typically each inverter includes a p-type pull-up (PU) transistor and an n-type pull-down (PD) transistor embedded in a substrate. The top surface of the substrate defines a substrate plane of the SRAM cell.
The PU and PD transistors of each inverter generally share a common gate structure. The common gate structure is operative to activate and deactivate the PU and PD transistors of each inverter simultaneously.
One source/drain (S/D) region of the PU transistor is connected to a voltage supply and the other S/D region is connected to a metal contact. One S/D region of the PD transistor is connected to a voltage ground and the other S/D region is connected to the same metal contact. The S/D regions that connect the PU and PD transistors of each inverter together are electrically connected together through the metal contact. This is because the p-type S/D region of the PU transistor and the n-type S/D region of the PD transistor cannot be connected directly together without forming an n-p junction. Therefore, to avoid the formation of such an n-p junction, the metal contact is utilized to provide electrical continuity between the S/D regions of the PU and PD transistors.
In order to cross-couple the first and second inverters, one cross-coupled contact of the SRAM cell electrically connects the common gate structure of the first inverter to the metal contact of the second inverter. Additionally the other cross-coupled contact of the SRAM cell electrically connects the common gate structure of the second inverter to the metal contact of the first inverter.
One of the pass gate transistors is connected to a bit line and the other to a bit line bar (herein collectively “the bit lines”). A word line enables the pass gate transistors to control data flow between the inverters and the bit lines during read and write operations.
SRAM cells are constantly being down-sized to meet increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits in semiconductor structures. As such, the transistors of the SRAM cells need to be ever more densely packaged within a given footprint of the substrate plane.
To overcome some of the technical challenges associated with down-sizing, prior art vertical SRAM cells using vertically extending transistors have been developed. These prior art vertical transistors have channels (such as a nanowire type channel, a fin type channel or the like) that extend vertically upwards from a bottom S/D region embedded in the substrate to an upper S/D region disposed above the substrate. A gate structure is disposed above the bottom S/D region and below the upper S/D region.
However, prior art cross-coupled contacts in prior art vertical SRAM cells extend around and between the edges and/or tips of the gate structures in order to be able to land on the metal contacts of the bottom S/D regions. The extension of the cross-coupled contacts between the gate structures increases the minimum distance between the gates structures relative to the substrate plane. Therefore, the overall minimum footprint that prior art vertical SRAM cells can be down-sized to is limited, at least in part, by the extension of the cross-coupled contacts between the gate structures.
Additionally, these prior art cross-coupled contacts physically abut the gate structures on only one side, rather than around the entire perimeter, of the cross-coupled contacts. This is because the opposing side of the cross-coupled contacts extend between the gate structures and over the metal contacts they must land on. As such, the area of contact between a prior art cross-coupled contact and the gate structure it connects to is limited to just one side of the abutting cross-coupled contact. This limited area of contact becomes increasingly problematic for the flow of electricity between inverters as the SRAM cells are increasingly down-sized.
Accordingly, there is a need for a vertical SRAM cell, and method of making the same, that includes cross-coupled contacts that do not extend between the gate structures and, therefore, do not limit the minimum distance between the gate structures. Additionally, there is a need to utilize the entire perimeter of the cross-coupled contact to make electrical contact with the gate structure.